In a successive approximation register (SAR) A/D converter, capacitors in an array are charged to the instantaneous value (voltage) of an analog input voltage signal (Vin) by operation of sampling switches. To complete a sampling operation, whereby a sampled voltage corresponding to the instantaneous value of the input voltage signal at a sampling instance is locked in, the sampling switches are opened. During a subsequent A/D conversion operation, the converter successively performs a series of bit tests, wherein conversion switches connected to the capacitors are controlled to effectively generate a series of comparison voltages that are compared to the sampled voltage to determine whether the sampled voltage is higher or lower than each generated comparison voltage. The series of generated comparison voltages successively narrows in on the sampled voltage, whereby a digital representation of the sampled voltage is derived. Typically, a starting value for each series of comparison voltages is at the middle of a full-scale input voltage range. If the sampled voltage is detected as being higher than this initial first comparison voltage, the first (most significant) bit of the digital representation is set to a one, and the second value in the series of comparison voltages is selected halfway between the initial comparison voltage and the upper limit of the input voltage range. If the sampled voltage is determined to be lower than this second comparison voltage, the second bit of the digital representation is set to a zero, and the third value in the series of comparison voltages is selected as halfway between the first and second values in the series of comparison voltages for setting the third bit in the digital representation. By repeating such an operation for each bit, the digital code being generated to represent the sampled value of the analog input voltage signal can be made to have any resolution.
Each switch for the A/D converter must be designed to handle the voltages that may appear at the device terminals during the sampling and the conversion operations. In the case of a SAR A/D converter, some conversion transistors may be subject to the difference between a positive reference voltage (Vref) and the lowest Vin, where the lowest Vin may be a negative voltage. Therefore, prior art SAR A/D converters have been realized using conversion transistors that have a reliability voltage limit (no breakdown) that exceeds the width of a full-scale input voltage range.
Transistors that are fabricated to withstand higher voltages (having higher reliability voltage limits) are generally slower or larger than lower voltage transistors. For example, the doping levels in higher voltage transistors are generally lowered to withstand higher voltages, and the doped regions are made larger. This increases on-resistance unless the transistor gates are made wider.
A/D converters preferably perform very rapid sampling and conversion operations. Therefore, there is a tradeoff between switching speed, size, and the requirement of the switches to handle the worst-case voltages.
FIG. 1 illustrates one type of prior art SAR A/D converter. A similar converter is described in U.S. Pat. No. 6,940,445, incorporated herein by reference for describing in detail the structure and operation of a converter that has a programmable input voltage range, where some of the full-scale input voltage ranges may extend above and/or below a reference voltage range (delimited by a low reference voltage potential and a high reference voltage potential). Circuitry for only three bits of resolution is shown explicitly in FIG. 1, although actual A/D converter implementations typically have much higher resolutions (say, 8, 12, 16, or 18 bits of resolution).
In FIG. 1, an analog input voltage signal Vin is to be sampled at a particular instant in time, and the sampled value is to be converted into a corresponding digital code. The maximum value of the digital code (all ones) corresponds to a maximum analog voltage, delimiting a full-scale input voltage range. The upper limit of the full-scale input voltage range may (but need not) equal the upper reference potential Vref. The minimum value of the digital code (all zeroes) corresponds to a minimum analog voltage, delimiting the full-scale input voltage range. The lower limit of the full-scale input voltage range may (but need not) equal the lower reference potential, 0 Volts. In the case where the upper and lower limits of the full-scale input voltage range are substantially equal to the upper and lower reference voltage potentials, there is no need to scale down the input voltage to the dynamic range of the converter. In such a case, the A/D converter of FIG. 1 successively compares the sampled voltage to different fractions of Vref and generates a digital code that substantially represents the ratio of the sampled voltage to Vref.
While Vin is being tracked prior to the sampling instance, sampling switches S1-S4 are on (closed), and conversion switches S5-S7 are off (open). Switches S5-S7 are three-way switches that are either off (open) or connecting the bottom plates of capacitors 2-4 to either the low reference potential or the high reference potential. The voltage across the binary weighted capacitors 2-4 (plus other capacitors not shown) therefore tracks the analog input voltage signal Vin. The capacitors 2-4 (and others not shown) are binary weighted having the values C/2, C/4, C/8, etc., respectively, where C is a predefined total capacitance quantity. Other types of capacitor arrays are known for a SAR A/D converter.
To complete a sampling operation, switches S1-S4 are opened to lock in a sampled voltage across capacitors 2-4 corresponding to the instantaneous value of the input voltage signal Vin at the sampling instance.
A SAR conversion engine and switch controller 5 (hereinafter controller 5) contains a successive approximation register (SAR) with an n-bit code that is updated at the end of each bit-test cycle. During each bit-test cycle, the sampled voltage is effectively compared to a comparison voltage corresponding to the n-bit code stored in the SAR. A first (most significant) bit is determined in the first bit-test cycle, which indicates whether the sampled voltage is above or below the first comparison voltage Vref/2. The controller 5 applies the individual comparison voltages, by controlling the conversion switches S5-S7 (and others not shown), to selectively couple the bottom plates of the capacitors to either the high reference potential (Vref) or the low reference potential (0 volts). Each capacitor corresponds to (is controlled according to) one corresponding bit in the SAR. The switching of the capacitors by the controller 5 redistributes the charges on the capacitor plates. For example, if the C/2 capacitor 2 is connected to the high reference voltage potential (Vref), and all the other capacitors are connected to the low reference potential (0 volts), then the voltage VX at the non-inverting input of the comparator 6 will substantially equal Vref/2-Vin. If VX is less than 0 volts, it is known that the sampled voltage is above Vref/2, and the first bit of the n-bit code in the SAR is set to one until the end of the conversion cycle. In each bit-test cycle, the polarity of VX is the same as the polarity of the comparison voltage being evaluated less the sampled voltage. The comparator 6 detects the polarity of VX, and the n bits in the SAR are determined sequentially one bit per bit-test cycle. The conversion process continues for all the binary weighted capacitors (each being controlled by one bit in the SAR) until the least significant bit has been determined, at which point the n-bit code in the SAR is the resulting digital code corresponding to the sampled value of the input voltage signal.
The controlling of the capacitors by a digital code creates a digital to analog converter (D/A converter, or DAC), within the A/D converter, whose output is successively compared to the sampled input voltage. There may be any number of capacitors in the DAC depending on the desired resolution. Many variations of the D/A converter implementation (e.g., segmentation) and the successive-approximation algorithm are known by those skilled in the art.
The converter of FIG. 1 can also be configured to receive and process (sample and convert to digital codes) input voltage signals greater than Vref. This is done by controlling the switches S1-S7 to sample the input voltage on only a predefined ratio of the capacitors and to couple the remainder of the capacitors to 0 volts during sampling. As a result, some capacitors will be charged to Vin and other capacitors will be charged to 0 volts at the sampling instance. The conversion operation is carried out as described previously. The polarity of voltage VX at the non-inverting terminal of comparator 6 now reflects the polarity of the comparison voltages designated in the SAR less a fraction (the predefined ratio smaller than one) of the sampled input voltage signal. Therefore, the sampled input voltage is effectively attenuated by the predefined ratio of the plate area sampling Vin to the plate area sampling 0 volts. The full-scale input voltage range that corresponds to this mode of operation is characterized by (delimited by) the input voltage levels that result in the maximum and minimum digital codes being produced by the conversion operation. Accordingly, the ADC can process input voltage signals with respect to full-scale input voltage ranges that exceed the reference voltage range.
Similarly, the ADC can be configured so that the full-scale input voltage range extends below the lower limit of the reference voltage range. This is accomplished by coupling the C/2 capacitor 2 to the high reference potential Vref during sampling, coupling the C/4 capacitor 3 to Vin during sampling, and coupling the remaining capacitors to the low reference potential, 0 volts, during sampling. The conversion operation is carried out as described previously. The polarity of voltage VX at the non-inverting terminal of comparator 6 now reflects the polarity of the comparison voltages designated in the SAR less a predetermined fraction of sampled input voltage signal plus a predetermined offset (or levelshift). The full-scale input voltage range that corresponds to this mode of operation is characterized by the input voltage levels that result in the maximum and minimum digital codes being produced by the conversion operation. Accordingly, the ADC can process input voltage signals with respect to full-scale input voltage ranges that extends above and/or below the limits of the reference voltage range. Such scaling is further described in U.S. Pat. No. 6,940,445, incorporated herein by reference.
In all cases, after sampling, the input voltage terminal is decoupled from the capacitors and the bottom plates of the capacitors are selectively biased at 0 volts or Vref during the conversion process to successively derive the digital code corresponding to the sampled input voltage with respect to the pertinent full-scale input range.
In the case where the input voltage signal Vin is between O-Vref, the maximum voltage across the switches S5-S7 is Vref, and the reliability voltage limits for switches S5-S7 need only meet this relatively modest requirement. If the range of Vin extended below 0 volts or above Vref, then greater voltages will appear across switches S5-S7 and the reliability limits of these switches S5-S7 must meet the associated increased requirements. As an example, a SAR ADC may be designed to operate with an upper reference voltage potential Vref of 5 volts. The SAR ADC may be configured and operate with a full-scale analog input voltage range from −10 volts to +10 volts. Therefore, the conversion switches (e.g., switches S5-S7 in FIG. 1) must have reliability voltage limits that allow voltages of at least 15V to appear across the terminals of switches S5-S7 during the sampling operation.
Transistor switches, such as MOSFET switches, that can handle higher voltages are generally slower and larger than lower voltage transistors. For some applications, sampling rates greater than one million conversion cycles per second are required, and each conversion cycle requires many bit-test cycles (each switching one of the conversion switches S5-S7) to generate the digital code. It is desirable that the conversion switches can be switched very fast to quickly generate the n-bit digital code representing the sampled value of the input voltage signal.
There are many variations of SAR A/D converters, some more complex than those described above, but the basic principle is the same.
FIG. 2 illustrates a differential SAR A/D converter, where the analog input voltage is a differential signal between Vinp (positive) and Vinn (negative). The average value of Vinp and Vinn (Vinp/2+Vinn/2) may be referred to as the common-mode voltage, which nominally is substantially constant. The difference between Vinp and Vinn may be referred to as the differential voltage (Vinp-Vinn), which is to be sampled and digitized. Each input terminal (Vinp and Vinn) has its own set of binary weighted capacitors C/2-C/64 for a 6-bit A/D converter. The sampling switches S, 9, and 10 are closed during the sampling operation until the sampling instance when these switches are opened. Conversion switches 11 and 12 are open during the sampling operation. The full-scale input voltage range can be changed/selected by modifying the operation of switches S, 9, 10, 11, and 12 during the sampling operation as described with respect to FIG. 1 (so that a certain ratio of the capacitors sample the input voltage signal and the other capacitors sample the reference potentials). During the conversion operation, a controller controls switches 11 and 12 to effectively generate a series of comparison voltages according to the contents of a SAR register. Comparator 13 evaluates each comparison voltage with respect to the sampled (and potentially scaled and offset) value of the input voltage signal in the same manner as described above. Further detail regarding the operation of a differential SAR A/D converter is provided in U.S. Pat. No. 6,667,707, incorporated herein by reference. The conversion switches 11 and 12 in FIG. 2, similar to those in FIG. 1, must be able to withstand relatively large voltages during the sampling operation if the input voltage signal exceeds the reference voltage range (e.g. if Vinp and Vinn swing in the range from −10 volts to +10 volts).
The inherent problems (lower speed, larger size, etc.) associated with conversion switches designed to tolerate high voltages (higher than Vref) applies to many types of A/D converters (including, but not limited to SAR A/D converters) as well as a wide range of signal-processing applications (e.g., switched-capacitor amplifiers and filters).
What is needed is a method and circuits, such as a SAR A/D converter, that allow for fast operation when processing an input signal that may exceed a voltage range (such as a reference voltage range) that is used to represent and process the signal after sampling.